1. Field of the Invention
The invention is related to printed circuit boards which support high frequency electronics, and in particular to techniques for reducing parasitic capacitance between board layers.
2. Description of the Related Art
Printed circuit boards (PCBs) have been employed for many years to physically support and interconnect electronic circuit elements: passive and active, analog and digital, of low-levels and high-levels of integration. At low operational frequencies, circuit impedances are typically mismatched. However, with high frequency circuits it is important to match source and load impedances to prevent reflections and signal degradation. At high frequencies, the conductive traces which route signals among various board-mounted components (whose electrical characteristics can largely be ignored at low frequencies), operate as microstrip transmission lines having a characteristic impedance Z.sub.0, which is given by: EQU Z.sub.0 =.sqroot.(L/C) (Eq. 1)
where L and C are the inductance and capacitance of the trace per unit length. Preferably, the impedance of the transmission lines matches that of the source and load; this condition provides maximum power transfer.
FIG. 1A is a cross-sectional view of two metal layers of a conventional multi-layer board (cut along section line 1A--1A in FIG. 1B) illustrating an RF signal layer 10 and an RF ground plane, 12, each typically about 0.7 mils (0.018 mm) thick (1/2 oz. (14.18 gm) plating) or 1.4 mils (0.0356 mm) thick (1 oz. (28.35 gm) plating), with a dielectric layer 14, commonly about 62 mils (1.57 mm) thick, sandwiched between the two RF layers. Signal layer 10 is composed of signal traces, with spaces between the traces; it is not a solid plane of conductive material. As illustrated in FIG. 1B, a 50.OMEGA. trace 15 such as would be found in the board's RF signal layer 10 (FIG. 1A) is about 120 mils (3.05 mm) wide. A surface-mount capacitor C1, 60 mils by 30 mils (1.52 mm.times.0.76 mm) in size, for example, is soldered to component mounting pads 16 and 18 and joins the illustrated trace segments. At 30 mils in width, C1 is substantially narrower than the traces. An equivalent circuit is illustrated in FIG. 1C, with the 50106 transmission lines 15 connecting capacitor C1 between a signal source V.sub.S having a source impedance R.sub.S of 50.OMEGA. and a load having an impedance R.sub.L of 50.OMEGA.. The component mounting pads 16 and 18 and the traces 15 to which they are connected are about the same width, and as such have no adverse affect on the line impedance.
As board densities increase, both the thickness of the board and the width of the circuit traces are reduced. FIG. 2A is a cross-sectional view of two metal layers of a much thinner multi-layer board (cut along section line 2A--2A in FIG. 2B) illustrating an RF signal layer 10 and an RF ground plane 12, each still about 0.7 mils (0.018 mm) thick, and a dielectric layer 14 which is only about 4 mils (0.102 mm) thick sandwiched between the two RF layers. At this dielectric thickness, a 50.OMEGA. transmission line 19 in the RF signal layer of FIG. 2A is about 7 mils (0.178 mm) wide, as illustrated in FIG. 2B, with capacitor C1 now substantially wider than the traces. The component mounting pads 16, 18 upon which the capacitor C1 is soldered are conventionally about 40 mils.times.40 mils (1.02 mm.times.1.02 mm) for 30 mil wide capacitor C1, with the pads' 5 mil overlap on either side of C1 needed to accommodate component placement and manufacturing tolerances. Now, however, because the pads are so much wider than the traces 19, the parasitic capacitance C.sub.P which exists between pads 16 and 18 and ground plane 12 can be significant, making a desired line impedance difficult to achieve and causing serious problems for high frequency signals. An equivalent circuit is shown in FIG. 2C: the parasitic capacitances C.sub.P to ground interfere with the intended operation of the circuit, generally causing it to have an undesirable low-pass response.
Specifications have been developed by the PCB industry for the manufacturing of boards intended for use with surface-mount components. The specifications allot a certain amount of board area, referred to as the "chip component size", for each resistor, inductor and capacitor to be placed on the board. For example, an "0603" board allots a nominal area of 60 mils.times.30 mils (1.52 mm.times.0.76 mm) for each component. 60 mils.times.30 mils capacitor C1 is an example of an "0603" component. An "0402" board allots 40 mils.times.20 mils (1.02 mm.times.0.51 mm) for each component, an "0805" board allots 80 mils.times.50 mils (2.03 mm.times.1.27 mm), and a "1206" board allots 120 mils.times.60 mils (3.05 mm.times.1.52 mm).
In conjunction with establishing standard chip component sizes, the PCB industry has also specified standard mounting pad dimensions for each component size, which define the size, shape and spacing of the component mounting pads to which the components are to be attached; these dimensions are referred to herein as the "conventional pad" dimensions.
Conventional pad dimensions are shown for three standard component sizes in FIGS. 3A-3C, with all dimensions shown in mils. A pair of conventional "0805" component mounting pads 20 and 21 is shown in FIG. 3A. Each pad has dimensions of 40 mils.times.50 mils (1.02 mm.times.1.27 mm), and is to be spaced 40 mils apart (1.02 mm). A pair of "0603" pads 22 and 23 is shown in FIG. 3B; each pad has dimensions of 40 mils.times.40 mils (1.02 mm.times.1.02 mm) and a spacing of 20 mils (0.51 mm). A pair of 30 mils.times.30 mils (0.76 mm.times.0.76 mm) "0402" pads 24 and 25 is shown in FIG. 3C, with a spacing of 20 mils. These industry standard pad dimensions were selected to insure a PCB's manufacturability, with consideration given to the tolerances allowed for component size, component placement and X-Y alignment, as well as to the pad's function of providing an electrically and mechanically sound solder joint. The specified dimensions are also intended to help control the positioning of a component for solder paste/reflow and to prevent component rotation or skewing; i.e., standard mounting pads allow a component to "self-align" on the pads as the solder cools.
However, because each of the industry standard pad sizes in FIGS. 3A-3C exceeds the width of a high-density board trace such as the 7 mil wide trace shown in FIG. 2B, their use contributes to the parasitic capacitance and impedance matching problems discussed above.
Similar problems can arise when an array of component mounting pads is arranged in a pattern to accommodate a multiple pin-out device. For example, the plan views of FIGS. 4A-4C show component mounting pad layouts and dimensions for use with three commercially available surface-mount filter packages, for which manufacturer's suggested component mounting pad sizes have been established. FIG. 4A shows a pad layout for a 4-pin 2.4 GHz L-C bandpass filter package made by the Murata Corp. in Smyrna, Ga. Two of the pads 26 have dimensions of 40 mils.times.60 mils (1.02 mm.times.1.52 mm) and two of the pads 28 are 48 mils.times.31 mils (1.22 mm.times.0.79 mm). FIG. 4B shows a pad layout for a 7-pin 2.4 GHz input bandpass resonator filter package made by Toko Corp. in Mt. Prospect, Ill., in which all pads 30 are 48 mils.times.31 mils (1.22 mm.times.0.79 mm). FIG. 4C shows a pad layout for a 12-pin 500 MHZ surface acoustic wave (SAW) filter package made by Sawtek Corp. in Orlando, Fla., in which all of the pads 32 are 36 mils.times.59 mils (0.91 mm.times.1.50 mm), with the exception of one slightly longer pad 34 of 36 mils.times.76 mils (0.91 mm.times.1.93 mm). The outlines of the various filter packages are shown as dashed lines in FIGS. 4A, 4B and 4C. Because the mounting pads are likely to be much larger than the signal traces found on a high density PCB, they can cause the same types of parasitic capacitance and impedance matching problems discussed above in connection with the industry standard component mounting pads.
PCBs made of exotic materials, such as "TEFLON"--derivative boards, are sometimes used to achieve good high frequency performance, but these boards tend to be very costly, and often cannot accommodate more than two layers.
Each component mounting pad which is wider than its PCB's signal traces tends to introduce an undesirable capacitance to a high frequency circuit design. It is therefore desirable to overcome the effects of this unwanted parasitic capacitance to accommodate high-density, high frequency circuit designs.